1. Field of the Invention
The present invention relates generally to charge pumps, and more particularly, to a circuit for controlling the charge pump ramp-up rate.
2. Problem to be Solved
Flash memory devices are typically nonvolatile memories that are reprogrammable. Such devices are Electrically Erasable Programmable Read Only Memories (EEPROM). Typically, the flash memory cells are arranged in an array and are located at the intersections of rows (word lines) and columns (bit lines). A cell is typically comprised of a floating gate transistor and a select transistor. The floating gate transistors are programmed by grounding the control electrode and raising the drain voltage. Tunneling causes electrons to be transferred from the substrate to the floating-gate through a thin tunneling oxide layer. A programming voltage pulse between about 18-20 volts may be needed to induce tunneling. As charge builds up on the floating gate, the electric field is reduced, decreasing electron flow. During programming, the select transistor is used to isolate the unselected memory cells that are located on the same column. Erasing of the memory cell is accomplished by applying a high programming voltage pulse to the control electrode of the floating-gate transistor.
High programming voltages result in overstress of the flash memory device. Such overstress limits the number of programming cycles performed on a flash memory device thereby shortening the useful lifetime of the memory device. The peak tunneling current has a direct bearing on the reliability and service life of the memory device. The peak tunneling current is directly related to the ramp-up rate of the programming voltage pulse outputted by a charge pump. If the ramp-up rate of the programming voltage pulse is too high, the peak tunneling current may overstress the thin tunneling oxide layer resulting in reduced reliability and shortened service life.
One attempt at solving the aforementioned problem is the utilization of a weak charge pump configuration. Such a configuration uses several pumps, each of which using smaller pump-capacitor values and lower pump-oscillator frequencies. However, for flash memory applications, the connection scheme of the charge pumps is complex, requires a relatively large chip area and consumes a relatively large amount of power. Furthermore, weak charge pumps provide a ramp-up rate that is too low thereby increasing the time required for programming and erasing operations.
Thus, it is an object of the present invention to provide a control circuit for accurately and efficiently controlling the ramp-up rate of a charge pump used for programming flash memory devices.
It is another object of the present invention to provide a control circuit for controlling the ramp-up rate of a charge pump used for programming and erasing a flash memory device so as to prevent overstressing the flash memory device.
It is a further object of the present invention to provide a control circuit for controlling the ramp-up rate of a charge pump that allows for the use of only one charge pump for performing operations on flash memory devices.
It is another object of the present invention to provide a control circuit for controlling the ramp-up rate of a charge pump which can be implemented with modern sub-half micron CMOS technology.